A FET can be fabricated on a bulk semiconductor substrate (planar devices) or on a silicon-on-insulator (SOI) type of structure, including extremely thin SOI (ETSOI) structures. In a replacement gate process a so-called dummy gate structure is formed from, for example, polysilicon (poly), source-drain (S/D) processing is initiated or continued and the dummy gate structure is removed and replaced by an electrically conductive metal-containing gate stack that overlies a channel region between the S/D in the bulk semiconductor substrate or in the silicon layer of the SOI structure.
One problem that can arise during the fabrication of replacement gate FET devices relates to the formation of S/D extension regions relative to the FET channel and the proper alignment and overlap of the S/D extensions.